Course Schedule and Catalog

Department: Electrical & Computer Eng.

8:00AM - 9:15AM TR DCH 1055 (21-AUG-2017 - 1-DEC-2017) 

6:30PM - 7:45PM W HRG 129 (21-AUG-2017 - 1-DEC-2017) 

Session: Full Term

Grade Mode: Standard Letter

Course Type: Lecture/Laboratory

Language of Instruction: Taught in English

Method of Instruction: Face to Face

Credit Hours: 4

 

Section Max Enrollment: 16

Section Enrolled: 10

Total Cross-list Max Enrollment: 140

Total Cross-list Enrolled: 130

Enrollment data as of: 29-SEP-2023 9:41AM

 

 

Final Exam: Scheduled Final Exam-OTR Room

12-DEC-2017  

7:00PM - 10:00PM T DCH 1055

 

12-DEC-2017  

7:00PM - 10:00PM T DCH 1046

 

 

Description: Evolution of key architecture concepts found in advanced uniprocessor systems. Fundamental and advanced pipelining techniques and associated issues for improving processor performance. Illustrated with RISC processors such as the ARM processor. Examine several metrics for processor performance, such as Amdahl’s law. Key concepts of data and program memory systems found in modern systems with memory hierarchies and cashes. Perform experiments in cache performance analysis. Influence of technology trends, such as Moore’s law, on processor implementation Approaches for exploiting instruction level parallelism, such as VLIW. Introduction to parallel and multicore architectures. Introduction to processor architectures targeted for imbedded applications.Additional coursework required beyond the undergraduate course requirements. Cross-list: ELEC 425, COMP 425, ELEC 425, COMP 425, ELEC 554, COMP 554, COMP 554, ELEC 425, COMP 425, ELEC 554, COMP 554. Mutually Exclusive: Cannot register for ELEC 554 if student has credit for ELEC 425.