Course Schedule - Fall Semester 2017

     

Meeting location information can now be found on student schedules in ESTHER (for students) or on the Course Roster in ESTHER (for faculty and instructors).
Additional information available here.

COMP 326 001 (CRN: 10512)

DIGITAL LOGIC DESIGN

Long Title: DIGITAL LOGIC DESIGN
Department: Computer Science
Instructor: Varman, Peter J.
Meeting: 10:50AM - 12:05PM TR (21-AUG-2017 - 1-DEC-2017) 
Part of Term: Full Term
Grade Mode: Standard Letter
Course Type: Lecture/Laboratory
Language of Instruction: Taught in English
Method of Instruction: Face to Face
Credit Hours: 3
Course Syllabus:
Course Materials: Rice Campus Store
 
Restrictions:
May not be enrolled in one of the following Level(s):
Graduate
Prerequisites: ELEC 220
Section Max Enrollment: 73
Section Enrolled: 1
Total Cross-list Max Enrollment: 73
Total Cross-list Enrolled: 52
Enrollment data as of: 12-JUN-2024 9:51AM
 
Additional Fees: None
 
Final Exam: Scheduled Final Exam-OTR Room
Final Exam Times:
7-DEC-2017  
9:00AM - 12:00PM R
 
7-DEC-2017  
9:00AM - 12:00PM R
 
 
Description: Study of gates, flip-flops, combinational and sequential switching circuits, registers, logical and arithmetic operations, introduction to the Verilog hardware description language. Cross-list: ELEC 326.