Course Schedule - Fall Semester 2017

     

COMP 326 001 (CRN: 10512)

DIGITAL LOGIC DESIGN

Long Title: DIGITAL LOGIC DESIGN
Department: Computer Science
Instructor: Varman, Peter J.
Meeting: 10:50AM - 12:05PM TR DCH 1070 (21-AUG-2017 - 1-DEC-2017) 
Session: Full Term
Grade Mode: Standard Letter
Course Type: Lecture/Laboratory
Method of Instruction: Face to Face
Credit Hours: 3
Course Syllabus:
Course Materials: Rice Campus Store
 
Restrictions:
May not be enrolled in one of the following Level(s):
Graduate
Prerequisites: ELEC 220
Section Max Enrollment: 73
Section Enrolled: 1
Total Cross-list Max Enrollment: 73
Total Cross-list Enrolled: 52
Enrollment data as of: 28-MAR-2020 7:27AM
 
Fees: None
 
Final Exam: Scheduled Final Exam-OTR Room
Final Exam Times:
7-DEC-2017  
9:00AM - 12:00PM R DCH 1070
 
7-DEC-2017  
9:00AM - 12:00PM R DCH 1075
 
 
Description: Study of gates, flip-flops, combinational and sequential switching circuits, registers, logical and arithmetic operations, introduction to the Verilog hardware description language.