Course Schedule - Fall Semester 2015

     

Meeting location information can now be found on student schedules in ESTHER (for students) or on the Course Roster in ESTHER (for faculty and instructors).
Additional information available here.

ELEC 554 001 (CRN: 13958)

COMPUTER SYSTEMS ARCHITECTURE

Long Title: COMPUTER SYSTEMS ARCHITECTURE
Department: Electrical & Computer Eng.
Instructor: Simar, Ray
Meetings:
2:00PM - 2:50PM MWF (24-AUG-2015 - 4-DEC-2015) 
7:00PM - 7:50PM M (24-AUG-2015 - 4-DEC-2015) 
Part of Term: Full Term
Grade Mode: Standard Letter
Course Type: Lecture/Laboratory
Language of Instruction: Taught in English
Method of Instruction: Face to Face
Credit Hours: 4
Course Syllabus:
 
Restrictions:
Must be enrolled in one of the following Level(s):
Graduate
Section Max Enrollment: 49
Section Enrolled: 16
Total Cross-list Max Enrollment: 49
Total Cross-list Enrolled: 48
Enrollment data as of: 16-APR-2024 9:06PM
 
Additional Fees: None
 
Final Exam: GR Course-Dept Schedules Exam
 
Description: Evolution of key architecture concepts found in advanced uniprocessor systems. Fundamental and advanced pipelining techniques and associated issues for improving processor performance. Illustrated with RISC processors such as the ARM processor. Examine several metrics for processor performance, such as Amdahl’s law. Key concepts of data and program memory systems found in modern systems with memory hierarchies and cashes. Perform experiments in cache performance analysis. Influence of technology trends, such as Moore’s law, on processor implementation Approaches for exploiting instruction level parallelism, such as VLIW. Introduction to parallel and multicore architectures. Introduction to processor architectures targeted for imbedded applications.Additional coursework required beyond the undergraduate course requirements. Cross-list: ELEC 425, COMP 425, COMP 554. Mutually Exclusive: Cannot register for ELEC 554 if student has credit for ELEC 425.