Course Schedule and Catalog
Course Schedule - Spring Semester 2027
Meeting location information can now be found on student schedules in ESTHER (for students) or on the Course Roster in ESTHER (for faculty and instructors).Additional information available here.
Meeting location information can now be found on student schedules in ESTHER (for students) or on the Course Roster in ESTHER (for faculty and instructors).Additional information available here.
ELEC 501 001 (CRN: 26676)
PROCESSOR MICROARCHITECTURE
Long Title: PROCESSOR MICROARCHITECTURE DESIGN AND IMPLEMENTATION
Department: Electrical & Computer Eng.
Instructor: Varman, Peter
Meeting: 10:50AM - 12:05PM TR (11-JAN-2027 - 23-APR-2027)
Part of Term: Full Term
Grade Mode: Standard Letter
Course Type: Lecture
Language of Instruction: Taught in English
Method of Instruction: Face to Face
Credit Hours: 3
Course Syllabus:
Course Materials: Rice Campus Store
Restrictions:
Must be enrolled in one of the following Level(s):
Graduate
Section Max Enrollment: 40
Section Enrolled: 0
Total Cross-list Max Enrollment: 40
Total Cross-list Enrolled: 0
Enrollment data as of: 2-NOV-2026 3:31AM
Final Exam: GR Course-Dept Schedules Exam
Description: The course covers the design and implementation of micro-architectural components of modern CPU and memory systems. Topics covered include static and dynamic pipelines, out-of-order execution, instruction speculation, reorder buffers, static and dynamic branch prediction, multi-threaded, VLIW, and vector processors, cache memory organization and implementation, and an introduction to multiprocessor cache coherence and virtual memory. The course will require Verilog implementations of several micro-architectural components and their integration into a working CPU. Additional course work required beyond the undergraduate course requirement. Cross-list: ELEC 428. Mutually Exclusive: Cannot register for ELEC 501 if student has credit for ELEC 428.