Course Schedule and Catalog

Department: Electrical & Computer Eng.

Meeting: 4:00PM - 5:15PM MW (11-JAN-2027 - 23-APR-2027) 

Part of Term: Full Term

Grade Mode: Standard Letter

Course Type: Lecture

Language of Instruction: Taught in English

Method of Instruction: Face to Face

Credit Hours: 3

 

Section Max Enrollment: 25

Section Enrolled: 0

Enrollment data as of: 2-NOV-2026 2:48AM

 

 

Final Exam: GR Course-Dept Schedules Exam

 

Description: This course offers an in-depth study of hardware verification methodologies, with a strong emphasis on SystemVerilog and the Universal Verification Methodology (UVM). Students will explore industry-standard verification techniques, such as constrained-random testing, functional coverage, assertion-based verification, and testbench automation. The course is designed to equip students with the essential skills for verifying complex System-on-Chip (SoC) and FPGA designs, preparing the students for careers in verification engineering. Students will spend a significant portion of the time writing and refining testbenches. Assignments and projects will provide hands-on experience with SystemVerilog and UVM-based verification environments, enabling students to gain practical experience in developing reusable, scalable, and efficient verification frameworks. Recommended Prerequisite(s): Strong foundation in digital design and proficiency in hardware description languages (HDLs) such as Verilog or VHDL and ELEC 521 or ELEC 526 or ELEC 527